FIG. 1 is a diagram illustrating a configuration example of a polyphase clock generating circuit. The polyphase clock generating circuit has a phase-locked loop (PLL) circuit including a phase-frequency detector 101, a low-pass filter 102, an oscillator 103 and a divider 104. The phase-frequency detector 101 compares a phase and a frequency of an output clock signal from the divider 104 and those of a reference clock signal CLK, and outputs a difference of the phases. The low-pass filter 102 averages the differences of the phases output by the phase-frequency detector 101 to output the resultant. The oscillator 103 generates and outputs a plurality of phases of clock signals φ1 to φp whose phases are adjusted so that an average value of the differences becomes small. The divider 104 divides a frequency of the clock signal φ1, for example, and outputs a clock signal whose frequency is lower than that of the clock signal φ1 to the phase-frequency detector 101 in a feedback manner. Through the feedback loop processing, the phase of the clock signal φ1 is soon converged to the same phase as that of the reference clock signal CLK, and the clock signal φ1 is locked.
The polyphase clock generating circuit in FIG. 1 has advantages that a system thereof is simple, and power consumption thereof is small. However, in the polyphase clock generating circuit in FIG. 1, the oscillator 103 is a ring oscillator, so that there are disadvantages that the noise characteristic is high, and it is not possible to achieve oscillation at a high frequency. Further, in the polyphase clock generating circuit in FIG. 1, it is possible to configure the oscillator 103 by using a plurality of inductors for solving the problems of noises and frequencies, but, there are disadvantages that area becomes very large, and cost is increased.
FIG. 2 is a diagram illustrating a configuration example of another polyphase clock generating circuit. The polyphase clock generating circuit in FIG. 2 corresponds to the polyphase clock generating circuit in FIG. 1 to which a delay line 201, a phase detector 202 and a low-pass filter 203 are added. The delay line 201, the phase detector 202 and the low-pass filter 203 configure a delay-locked loop (DLL) circuit. Here, the oscillator 103 outputs a single-phase clock signal to the divider 104, the delay line 201 and the phase detector 202. The delay line 201 delays an output clock signal from the oscillator 103 to output a plurality of phases of clock signals φ1 to φp. The phase detector 202 compares a phase of the output clock signal from the oscillator 103 and that of the clock signal φ1, for example, and outputs a difference of the phases to the low-pass filter 203. The low-pass filter 203 averages the differences of the phases to output the resultant to the delay line 201. The delay line 201 generates and outputs a plurality of phases of clock signals φ1 to φp whose phases are adjusted so that the difference of the phases output by the low-pass filter 203 becomes small. Through processing of the delay-locked loop circuit, the phase of the clock signal φ1 is soon converged to the same phase as that of the reference clock signal CLK, and the clock signal φ1 is locked.
The polyphase clock generating circuit in FIG. 2 has an advantage that the noise characteristic of the phase-locked loop circuit can be improved by configuring the oscillator 103 using one inductor. However, since the polyphase clock generating circuit in FIG. 2 needs the two low-pass filters 102 and 203, there is a disadvantage that a circuit area becomes very large.
Further, there is known a time-to-digital converter in which a coarse time converter, a first fine time register and a second fine time register are provided, and a coarse time conversion and a fine time conversion are combined (refer to Patent Document 1 and Patent Document 2, for example).
Patent Document 1: Japanese National Publication of International Patent Application No. 2009-527157
Patent Document 2: Japanese National Publication of International Patent Application No. 2009-527158